A top gate type TFT is a thin-film transistor structure frequently used in a device including an active matrix structure (referred to as an active matrix device, hereinafter). Such frequent use of the top gate type TFT is attributed to the fact that as it can be manufactured with a smaller number of manufacturing process than that for a conventional bottom gate type TFT, TFT manufacturing costs and thus manufacturing costs of the active matrix device can be reduced. As a device using such an active matrix structure, a liquid crystal display or an electroluminescence display (EL display) using an oxide or an organic material can be cited.
In the conventional manufacturing process of the top gate type TFT, P doping is normally carried out by using phosphine (PH3) to form a contact layer. In this process, source and drain electrodes are doped with P by spraying plasma generated by gas containing PH3 on the surfaces of the source and drain electrodes. In the region doped with P, the doped P species migrate during the formation of an Amorphous Silicon (a-Si) layer carried out after P doping, and the corresponding region forms an n+ layer.
During the P doping, PH3 is used as described above, and chemical species containing P are generated by forming plasma. Thus, chemical species containing P remain in a processing chamber for performing each following processes, in most cases in the inner wall of a vacuum container. Such chemical species containing P left in the inner wall of the processing chamber are taken in an a-Si layer or a gate insulating film during the formation of the Amorphous Silicon (a-Si) layer or an Silicon Nitride (SiNx) layer used as the gate insulating film, which is carried out after P doping. Consequently, an OFF-state current of the TFT is deteriorated.
To remove such an adverse effect of the P doping step, the conventional manufacturing process of the top gate type TFT generally employs a method of using a typical single wafer CVD device, executing P doping and formation of an a-Si layer and a gate insulating film in a plurality of different processing chambers, and then carrying a substrate doped with P among these processing chambers in vacuum.
However, in the foregoing manufacturing method of the top gate type TFT using the plurality of processing chambers, the deterioration of TFT characteristics is inevitable. This problem occurs because of the sticking of so-called degassed components to the a-Si layer and the gate insulating film. Such degassed components are emitted from the inner wall of the processing chamber to both surfaces of the source and drain electrodes during vacuum-carrying from one processing chamber to another.
The top gate type TFT can be manufactured without such inconvenience by using a plurality of different processing chambers, e.g., two processing chambers, to execute P doping and form an a-Si layer and a gate insulating layer, respectively. However, the use of two processing chambers may reduce TFT throughput, leading to a considerable reduction in productivity, and manufacturing costs for an active matrix device including the top gate type TFT may even be raised.
Considering the foregoing problems, there is a need to provide a manufacturing method and a manufacturing apparatus, which are capable of preventing any adverse effects from being given to TFT characteristics, improving productivity, and reducing manufacturing costs for an active matrix device including a top gate type TFT.